High-speed low-power CMOS comparator dedicated to 10 bit 20 MHz pipeline ADCs for RF WLAN applications

被引：9

作者：

Guermaz, M. B. ^{[1
]}

Bouzerara, L. ^{[1
]}

Belaroussi, M. T. ^{[1
]}

Slimane, A. ^{[1
]}

Lehouidj, B. ^{[2
]}

机构：

[1] Ctr Dev Technol Avancees, Microelect & Nanotechnol Div, Algiers, Algeria

[2] Univ Sci & Technol Houari Boumediene, Instrumentat Lab, Fac Elect & Comp Engn, Bab Ezzouar Algiers, Algeria

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 2008年 / 95卷 / 09期

关键词：

pipeline ADC; comparator; dynamic latch; offset; switched capacitor network; bottom plate technique;

D O I：

10.1080/00207210801931540

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article describes and analyses a low power and high speed comparator. The designed comparator is intended to be implemented in a 10 bit 20MHz Pipeline Analogue-to-Digital Converter dedicated to RF Wireless Local Area Network (WLAN) applications. This comparator is based on the switched capacitor network using a two-phase non-overlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8 mm CMOS AMS process parameters, with a power supply voltage of 5V and an input common mode of 2-3 V, show that this comparator exhibits a propagation delay of 17.3 ns, an offset voltage of about 77.3 mV, a good accuracy and a low power consumption of about 0.8mW. The predicted performance is verified by analyses and simulations using PSPICE tool.

引用

页码：869 / 878

页数：10

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