3-D effect of cell designs on the breakdown voltage of power SOI-LDMOS

被引：6
|
作者：
Suzuki, Y [1 ]
Kishida, T [1 ]
Takano, H [1 ]
Shirai, Y [1 ]
Suzumura, M [1 ]
机构：
[1] MATSUSHITA ELECT WORKS INC,CENT RES LAB,KADOMA,OSAKA 571,JAPAN
来源：
1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/SOI.1996.552530
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：134 / 135
页数：2
相关论文
共 50 条
  • [31] A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region
    Zhang, Wentong
    Li, Lu
    Qiao, Ming
    Zhan, Zhenya
    Cheng, Shikang
    Zhang, Sen
    He, Boyong
    Luo, Xiaorong
    Li, Zhaoji
    Zhang, Bo
    IEEE ELECTRON DEVICE LETTERS, 2019, 40 (07) : 1151 - 1154
  • [32] Improve the Dynamic Breakdown Voltage of SOI LDMOS Devices by Eliminating the Effect of Deep Depletion in Substrate
    Cai, Yu
    2021 3RD ASIA ENERGY AND ELECTRICAL ENGINEERING SYMPOSIUM (AEEES 2021), 2021, : 11 - 14
  • [33] Large-signal analysis of substrate effects in RF-power SOI-LDMOS transistors
    Vestling, Lars
    Bengtsson, Olof
    Eklund, Klas-Hakan
    Olsson, Jorgen
    SOLID-STATE ELECTRONICS, 2010, 54 (02) : 171 - 177
  • [34] The Effect of Dual Dummy Gate in the Drift Region on the on-State Performance of SOI-LDMOS Transistor for Power Amplifier Application
    Sahoo, Jagamohan
    Mahapatra, Rajat
    SILICON, 2022, 14 (05) : 2039 - 2050
  • [35] The Effect of Dual Dummy Gate in the Drift Region on the on-State Performance of SOI-LDMOS Transistor for Power Amplifier Application
    Jagamohan Sahoo
    Rajat Mahapatra
    Silicon, 2022, 14 : 2039 - 2050
  • [36] A Bulk Full-Gate SOI-LDMOS Device With Bulk Channel and Electron Accumulation Effect
    Chen, Weizhong
    Qin, Haifeng
    Huang, Yuanxi
    Huang, Yi
    Han, Zhengsheng
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (12) : 6286 - 6291
  • [37] Modeling of Breakdown Voltage for SOI Trench LDMOS Device Based on Conformal Mapping
    Wang, Yanan
    Wang, Zhigang
    Bai, Tianrui
    Kuo, James B.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (03) : 1056 - 1062
  • [38] Enhancement of breakdown voltage for SOI RESURF LDMOS employing a buried air structure
    Kim, SH
    Park, IY
    Choi, YI
    Chung, SK
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2001, 39 : S39 - S41
  • [39] Effect of Drift Length on Shifts in 400-V SOI LDMOS Breakdown Voltage Due to TID
    Shu, Lei
    Zhao, Yuan-Fu
    Galloway, Kenneth F.
    Wang, Liang
    Wang, Xin-Sheng
    Yuan, Zhang-Yi'an
    Zhou, Xin
    Chen, Wei-Ping
    Qiao, Ming
    Wang, Tian-Qi
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2020, 67 (11) : 2392 - 2395
  • [40] Analytical model for the ideal breakdown voltage and optimum doping profile of SOI RESURF LDMOS
    He, J
    Zhang, X
    Huang, R
    Wang, YY
    CHINESE JOURNAL OF ELECTRONICS, 2001, 10 (02): : 210 - 213
12345