A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process

被引:6
|
作者
Mahmoud, Ahmed [1 ]
Fanori, Luca [1 ,2 ]
Mattsson, Thomas [3 ]
Caputa, Peter [4 ]
Andreani, Pietro [1 ]
机构
[1] Lund Univ, Lund, Sweden
[2] Marvell Italy, Pavia, Italy
[3] Ericsson Modems, Lund, Sweden
[4] Ericsson AB, Lund, Sweden
关键词
8-Shaped; Magnetic coupling; VCO; Class-B; Reconfigurable core; Low phase noise; One octave; UTBB FD-SOI CMOS; WIDE-TUNING-RANGE;
D O I
10.1007/s10470-016-0759-4
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A 2.8-to-5.8 GHz harmonic VCO designed in a 28 nm UTBB FD-SOIC MOS process adopts a reconfigurable active core to save power at the lower oscillation frequencies, and to enable a trade-off between power consumption and phase noise at all frequencies. Interference caused by the magnetic coupling to and from the VCO inductor is greatly attenuated by resorting to an inductor in the shape of an 8. Simulations of the magnetic coupling between an 8-shaped inductor and a reference inductor show a reduction in magnetic coupling as high as 44 dB, depending also on size, orientation, and shape of the reference inductor. The UTBB FD-SOI CMOS process is instrumental to achieve a tuning range in excess of one octave at low power consumption. The VCO operates from 0.9 V and has a figure-of-merit of 186-189 dBc/Hz, depending on the oscillation frequency and the configuration of the oscillator core. The active area of the VCO is 380 x 700 mu m.
引用
收藏
页码:391 / 399
页数:9
相关论文
共 50 条
  • [31] Two-Path 77-GHz PA in 28-nm FD-SOI CMOS for Automotive Radar Applications
    Nocera, Claudio
    Papotto, Giuseppe
    Palmisano, Giuseppe
    ELECTRONICS, 2022, 11 (08)
  • [32] A 3 GHz Dual Core Processor ARM CortexTM-A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization
    Jacquet, David
    Hasbani, Frederic
    Flatresse, Philippe
    Wilson, Robin
    Arnaud, Franck
    Cesana, Giorgio
    Di Gilio, Thierry
    Lecocq, Christophe
    Roy, Tanmoy
    Chhabra, Amit
    Grover, Chiranjeev
    Minez, Olivier
    Uginet, Jacky
    Durieu, Guy
    Adobati, Cyril
    Casalotto, Davide
    Nyer, Frederic
    Menut, Patrick
    Cathelin, Andreia
    Vongsavady, Indavong
    Magarshack, Philippe
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (04) : 812 - 826
  • [33] Design and Evaluation of a 10 GHz LNA with Balun and Diodes for HBM and CDM ESD Protection in 28 nm CMOS FD-SOI
    Guedes, Thalis Da C.
    Bourgeat, Johan
    Barragan, Manuel J.
    Duchamp, Jean-Marc
    Ferrari, Philippe
    2024 37TH SBC/SBMICRO/IEEE SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2024, 2024, : 60 - 64
  • [34] A 28GHz Self-Contained Power Amplifier for 5G applications in 28nm FD-SOI CMOS
    Moret, Boris
    Knopik, Vincent
    Kerherve, Eric
    2017 IEEE 8TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2017,
  • [35] Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology
    Olivera, Fabian
    Petraglia, Antonio
    MICROELECTRONICS JOURNAL, 2018, 78 : 94 - 100
  • [36] Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology
    Tang, Xinyan
    Liu, Yao
    Mangraviti, Giovanni
    Zong, Zhiwei
    Khalaf, Khaled
    Zhang, Yang
    Wu, Wei-Min
    Chen, Shih-Hung
    Debaillie, Bjorn
    Wambacq, Piet
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2021, 69 (06) : 2841 - 2853
  • [37] Down-converter solutions for 77-GHz automotive radar sensors in 28-nm FD-SOI CMOS technology
    Nocera, Claudio
    Cavarra, Andrea
    Ragonese, Egidio
    Palmisano, Giuseppe
    Papotto, Giuseppe
    2018 14TH CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME 2018), 2018, : 153 - 156
  • [38] A 28 GHz Static CML Frequency Divider with Back-Gate Tuning on 22-nm CMOS FD-SOI Technology
    Hietanen, Mikko
    Aikio, Janne
    Akbar, Rehman
    Rahkonen, Timo
    Parssinen, Aarno
    2019 IEEE 19TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF), 2019, : 328 - 330
  • [39] 0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI
    Asprilla, Andres
    Cathelin, Andreia
    Deval, Yann
    IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023, 2023, : 269 - 272
  • [40] A Highly Linear 4-bit DAC with 1 GHz Sampling Rate Implemented in 28 nm FD-SOI Process
    Jaworski, Zbigniew
    PROCEEDINGS OF THE 24TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS - MIXDES 2017, 2017, : 189 - 195