Reformatting test patterns for testing embedded core based system using Test Access Mechanism (TAM) switch

被引：0
|
作者：
Basu, S
Mukhopadhay, D
Roychoudhury, D
Sengupta, I
Bhawmik, S
机构：
来源：
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2002年
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In the present paper a new algorithm for reformatting the test vector of System On Chip (SOC) with Test Access Mechanism (TAM) has been proposed. Exhaustive experimentation has been done by employing random reformatted test vectors to a variety of SOCs, constructed with the ISCAS sequential benchmark circuits. For a limited number of input pins, which has been provided for testing the SOC, the proposed algorithm reduces drastically the test-time as well as the hardware.
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页码：598 / 603
页数：4
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