Reformatting test patterns for testing embedded core based system using Test Access Mechanism (TAM) switch

被引：0
|
作者：
Basu, S
Mukhopadhay, D
Roychoudhury, D
Sengupta, I
Bhawmik, S
机构：
来源：
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In the present paper a new algorithm for reformatting the test vector of System On Chip (SOC) with Test Access Mechanism (TAM) has been proposed. Exhaustive experimentation has been done by employing random reformatted test vectors to a variety of SOCs, constructed with the ISCAS sequential benchmark circuits. For a limited number of input pins, which has been provided for testing the SOC, the proposed algorithm reduces drastically the test-time as well as the hardware.
引用
收藏
页码：598 / 603
页数：4
相关论文
共 50 条
  • [21] Genetic algorithm based test scheduling and test access mechanism design for system-on-chips
    Chattopadhyay, S
    Reddy, KS
    16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 341 - 346
  • [22] Software-Based Embedded Core Test Using Multi-Polynomial for Test Data Reduction
    Kang, Soyeon
    Choi, Inhyuk
    Lim, Hyeonchan
    Seo, Sungyoul
    Kang, Sangho
    2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2016, : 39 - 40
  • [23] Embedded core test generation using broadcast test architecture and netlist scrambling
    Jiang, JH
    Jone, WB
    Chang, SC
    Ghosh, S
    IEEE TRANSACTIONS ON RELIABILITY, 2003, 52 (04) : 435 - 443
  • [24] Combining visual TEST with ICE for embedded system testing
    Finkelman, D
    NINETEENTH CONVENTION OF ELECTRICAL AND ELECTRONICS ENGINEERS IN ISRAEL, 1996, : 160 - 161
  • [25] Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core
    Zhang Ling
    Kuang Ji-shun
    You Zhi-qiang
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, PT 2, PROCEEDINGS, 2010, 6082 : 434 - +
  • [26] Motor mechanism in Separation Test of Coal Mine Isolation Switch and Controllability Test System
    Zhang, Hongkui
    Lang, Fucheng
    Wang, Hao
    PROCEEDINGS OF THE 2016 4TH INTERNATIONAL CONFERENCE ON MECHANICAL MATERIALS AND MANUFACTURING ENGINEERING (MMME 2016), 2016, 79 : 870 - 873
  • [27] Risk-Based Vulnerability Testing Using Security Test Patterns
    Botella, Julien
    Legeard, Bruno
    Peureux, Fabien
    Vernotte, Alexandre
    LEVERAGING APPLICATIONS OF FORMAL METHODS, VERIFICATION AND VALIDATION: SPECIALIZED TECHNIQUES AND APPLICATIONS, PT II, 2014, 8803 : 337 - 352
  • [28] Efficient test data decompression for system-on-a-chip using an embedded FPGA core
    Zeng, G
    Ito, H
    18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 503 - 510
  • [29] Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores
    Han, Taewoo
    Choi, Inhyuk
    Kang, Sungho
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (08) : 1439 - 1447
  • [30] Test access proposal for core-based ICs
    Novellino, J
    ELECTRONIC DESIGN, 1998, 46 (01) : 102 - 102
12345