Characterization of Advanced Gate Architecture Stress on 22nm Gate-Last CMOS Device

被引：0
|
作者：
Fu, Zuozhen [1 ]
Ma, Xiaolong [1 ]
Yin, Huaxiang [1 ]
机构：
[1] Chinese Acad Sci, Key Lab Microelect Devices & Integrated Technol, Inst Microelect, Beijing 100029, Peoples R China
来源：
CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012) | 2012年 / 44卷 / 01期
关键词：
D O I：
10.1149/1.3694398
中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
In this paper, the characteristics of gate strain enginnering on 22nm High-k/Metal-Gate-last (HK/MG-last) CMOS device are studied through a process and device simulation by Sentarus TCAD tools. Advanced gate architecture with different tensile stress values (0 similar to 6GPa) was implemented into the simulation. Besides the traditional stressors like e-GeSi, capping layer and spacer, the stress from advanced gate architecture introduce a new stress effect on carriers tranporting in HK/MG-last device. The parameters optimization for metal gate architecture and material are carried out to maximize channel center strain effect along XX direction, which bring more enhancements on device's electrical performance. The results indicated that, compared to nitride stress liner, as the scaling of the gate length from 45nm to 22nm node, the channel stress caused by gate stressor is more obvious.
引用
收藏
页码：779 / 784
页数：6
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