A Process-Technology-Scaling-Tolerant Pipelined ADC Architecture Achieving 6-bit and 4 GS/s ADC in 45nm CMOS

A process-technology-scaling-tolerant pipelined ADC architecture has been demonstrated achieving 4 GS/s and 6-bit resolution in 45nm SOI CMOS. It utilizes open-loop, op-amp-less residue amplifier stages employing background master-slave gain calibration in order to achieve 4 GS/s clock rates while maintaining compatibility with deeply scaled CMOS processes. The pipelined ADC consumes 38 mW of power from a 1.4 V supply while operating at 4 GS/s and occupies a core area of only 0.04 mm 2 due to its use of compact open-loop residue amplifiers. The measured DNL and INL are -0.8/1.0 LSB and -1.0/0.9 LSB, respectively. The ADC SNDR at 4 GS/s is 31.6 dB with a 250 MHz input and 27.3 dB with a 1.8 GHz input.