Analysis of Negative Differential Resistance and RF/Analog Performance on Drain Engineered Negative Capacitance Dual Stacked-Source Tunnel FET

In this article, we systematically investigate the impact of ferroelectric (FE) layer thickness (tFE) on the electrical parameters of a negative capacitance dual stacked-source tunnel field-effect transistor (NCDSS-TFET) using TCAD simulator. The increase in tFE leads to higher ION/IOFF current ratio and better subthreshold swing (SS) with negligible hysteresis. However, increasing FE layer thickness also introduces negative differential resistance (NDR) which is undesirable for analog circuit applications. The NCDSS-TFET device is further optimized to eliminate NDR effects by engineering the drain. The analog/RF performance of the drain-engineered NCDSS-TFET such as transconductance (g(m)), output conductance (g(d)), intrinsic gain (g(m)/g(d)), cutoff frequency (fT), and intrinsic delay ( tau) is investigated. Analysis reports that the analog/RF parameters are improved by increasing the drain underlap length, thus ensuring the drain-engineered NCDSS-TFET suitable for high-performance and ultralow power analog applications.