An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-psrms-Integrated-Jitter Degradation With SSC Capability

被引:2
|
作者
Motozawa, Atsushi [1 ]
Hiraku, Yasuyuki [1 ]
Hirai, Yoshitaka [1 ]
Hiyama, Naoaki [1 ]
Imanaka, Yusuke [1 ]
Morishita, Fukashi [1 ]
机构
[1] Renesas Elect Corp, IoT & Infrastruct Business Unit, Tokyo 1878588, Japan
来源
关键词
Phase locked loops; Voltage-controlled oscillators; Clocks; Generators; Global navigation satellite system; Pulse generation; Industries; Electromagnetic interference (EMI); fractional divider (FDIV); fractional spur; fractional-N PLL (Frac-N PLL); integer-N PLL (Int-N PLL); phase interpolator (PI); spread-spectrum clocking (SSC);
D O I
10.1109/LSSC.2023.3254521
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Phase-locked loops (PLLs) are utilized in SoCs for the automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid electromagnetic interference (EMI). Recently, the global navigation satellite system (GNSS) is becoming more common and available frequency bands for clocks are getting narrow. That leads, in many products, replacement integer-N PLLs (Int-N PLLs) with fractional-N PLLs (Frac-N PLLs) are needed to obtain smaller output frequency steps than reference frequency. The attachable fractional divider proposed in this letter transforms an Int-N PLL into a Frac-N PLL with only 0.35 psrms of integrated RMS jitter degradation.
引用
收藏
页码:69 / 72
页数:4
相关论文
共 50 条
  • [1] Fast-lock hybrid PLL combining fractional-N and integer-N modes of differing bandwidths
    Woo, Kyoungho
    Liu, Yong
    Nam, Eunsoo
    Ham, Donhee
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (02) : 379 - 389
  • [2] A modified pulse swallow frequency divider for fractional-N PLL
    Yan, Peihui
    Jiang, Jinguang
    Liu, Jianghua
    Tang, Yanan
    IEICE ELECTRONICS EXPRESS, 2020, 17 (18) : 1 - 5
  • [3] Fractional-N PLL with multi-element fractional divider for noise reduction
    Sanyal, Arindam
    Yu, Xueyi
    Zhang, Yanlong
    Sun, Nan
    ELECTRONICS LETTERS, 2016, 52 (10) : 809 - 810
  • [4] A 14nm Fractional-N Digital PLL with 0.14psrms Jitter and-78dBc Fractional Spur for Cellular RFICs
    Yao, Chih-Wei
    Loke, Wing Fai
    Ni, Ronghua
    Han, Yongping
    Li, Haoyang
    Godbole, Kunal
    Zuo, Yongrong
    Ko, Sangsoo
    Kim, Nam-Seog
    Han, Sangwook
    Jo, Ikkyun
    Lee, Joonhee
    Han, Juyoung
    Kwon, Daehyeon
    Kim, Chulho
    Kim, Shinwoong
    Son, Sang Won
    Cho, Thomas Byunghak
    2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 422 - 422
  • [5] Optimized System Design for Fully Integrated Fractional-N PLL
    Zhu, Yuchun
    Jin, Jing
    Yu, Xiaopeng
    Zhou, Jianjun
    PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009), 2009, : 540 - 543
  • [6] Implementation of a Digital ΔΣ Modulator and Programmable Prescaler Divider Circuit for a Fractional-N PLL
    Hati, Manas Kumar
    Bhattacharyya, Tarun K.
    2016 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMPUTING AND COMMUNICATIONS (MICROCOM), 2016,
  • [7] A 56-GHz Fractional-N PLL With 110-fs Jitter
    Zhao, Yu
    Memioglu, Onur
    Kong, Long
    Razavi, Behzad
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 58 (01) : 57 - 67
  • [8] A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
    Mercandelli, Mario
    Santiccioli, Alessio
    Parisi, Angelo
    Bertulessi, Luca
    Cherniak, Dmytro
    Lacaita, Andrea L.
    Samori, Carlo
    Levantino, Salvatore
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (02) : 505 - 517
  • [9] A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
    Mercandelli, Mario
    Santiccioli, Alessio
    Parisi, Angelo
    Bertulessi, Luca
    Cherniak, Dmytro
    Lacaita, Andrea Leonardo
    Samori, Carlo
    Levantino, Salvatore
    2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, : 274 - +
  • [10] Fast-locking integer/fractional-N hybrid PLL frequency synthesizer
    Woo, Kyoungho
    Ham, Donhee
    IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 674 - +