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- [21] A CMOS 434/868 MHz FSK/OOK Transmitter with Integrated Fractional-N PLL 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 546 - 549
- [22] An Analog Enhanced All Digtial RF Fractional-N PLL With Self-Calibrated Capability PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008, : 749 - 752
- [24] A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC 2020 IEEE SYMPOSIUM ON VLSI CIRCUITS, 2020,
- [25] A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC 2024 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, CICC, 2024,
- [26] A 2.7-to-4.3GHz, 0.16psrms-Jitter,-246.8dB-FOM, Digital Fractional-N Sampling PLL in 28nm CMOS 2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 174 - U236
- [29] A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique IEEE SOLID-STATE CIRCUITS LETTERS, 2025, 8 : 45 - 48