Performance-driven Routing Tree Construction with Buffer Insertion and Wire Sizing

被引：0
|
作者：
祁昶
王高峰
机构：
[1] Institute of Microelectronics and Information Technology Wuhan University
[2] Wuhan 430072 China Wuhan 430072 China
[3] Institute of Microelectronics and Information Technology Wuhan University
来源：
Journal of Shanghai Jiaotong University | 2008年 / 01期
基金：
中国国家自然科学基金;
关键词：
performance-driven; multi-terminals net; rectilinear Steiner tree; buffer insertion; wiresizing optimization; RLC delay model;
D O I：
暂无
中图分类号：
TN405 [制造工艺];
学科分类号：
摘要：
A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances include the timing delay and the quality of signal waveform. The experimental results show that our proposed approach is scalable and obtains better performance than SP-tree and graph-RTBW approaches for the test signal nets.
引用
收藏
页码：46 / 51
页数：6
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