A NEW PERFORMANCE-DRIVEN GLOBAL ROUTING ALGORITHM FOR GATE ARRAY

This paper proposes a performance-driven global routing algorithm for Gate Array based on critical path-based tinting analysis method in contrast to the traditional net-based approach. The problem is formulated as a multi-commodity multi-terminal global routing problem with integer flows under additional timing constraints. The initial trees for global routing are generated by two net-based performance-driven Steiner tree algorithms and are routed simultaneously using the multi-commodity approach. Later, some nets are rerouted to release over-congested channels. As long as the total - accumulated delays on the critical paths affected by the nets still satisfy the constraints on the paths, the rerouted trees are accepted. This is the major difference between our present approach and previous net-based timing analysis methods, which may reject the rerouted tree of the net unnecessarily and result in increase of channel density and chip area. The experimental results based on MCNC (ISCAS) benchmarks show that our critical path-based method can obtain the same chip size as those which ignore timing completely, while achieving comparable path delay with the net-based method.