A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

被引：0

作者：

Wang Yu ^{[1
,2
]}

Yang Haigang ^{[1
]}

Cheng Xin ^{[2
]}

Liu Fei ^{[1
]}

Yin Tao ^{[1
]}

机构：

[1] Institute of Electronics, Chinese Academy of Sciences

[2] Graduate University of Chinese Academy of Sciences

来源：

Journal of Electronics(China) | 2012年 / 29卷 / 05期

关键词：

Pipelined Analog-to-Digital Converter (ADC); Foreground digital calibration; Gain error; Error estimation;

D O I：

暂无

中图分类号：

TN792 [];

学科分类号：

摘要：

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

引用

页码：445 / 450

页数：6

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