PLACEMENT ALGORITHM FOR A GATE ARRAY LSI.

被引:0
|
作者
Harada, Ikuo [1 ]
Kimoto, Tsutomu [1 ]
Tsukiyama, Shuji [1 ]
Shirakawa, Isao [1 ]
机构
[1] Osaka Univ, Faculty of Engineering,, Suita, Jpn, Osaka Univ, Faculty of Engineering, Suita, Jpn
关键词
D O I
暂无
中图分类号
学科分类号
摘要
14
引用
收藏
页码:51 / 59
相关论文
共 50 条
  • [1] NEW GLOBAL ROUTER FOR GATE ARRAY LSI.
    Tsukiyama, Shuji
    Harada, Ikuo
    Fukui, Masahiro
    Shirakawa, Isao
    1600, (CAD-2):
  • [2] APPROACH TO POLYCELL PLACEMENT FOR LSI.
    Sha Lu
    Tang Pushan
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 1984, 5 (04): : 412 - 421
  • [3] BIPOLAR 2500-GATE SUBNANOSECOND MASTERSLICE LSI.
    Nakaya, Masao
    Kato, Shuichi
    Tsukamoto, Katsuhiro
    Sakurai, Hiromi
    Kondo, Takashi
    Horiba, Yasutaka
    IEEE Journal of Solid-State Circuits, 1981, SC-16 (05): : 558 - 562
  • [4] EFFICIENT PLACEMENT AND ROUTING TECHNIQUES FOR MASTER SLICE LSI.
    Shiraishi, Hiroshi
    Hirose, Fumiyasu
    Jahrbuch der Schiffbautechnischen Gesellschaft, 1980, : 458 - 464
  • [5] SEMICUSTOM LSI.
    Kuramitsu, Yoichi
    Ueda, Masahiro
    Mitsubishi Electric Advance, 1985, 33 : 4 - 5
  • [6] ATE FOR VLSI/LSI.
    Anon
    Evaluation Engineering, 1984, 23 (09): : 54 - 71
  • [7] LSI GATE PLACEMENT PROGRAM ALPS
    WADA, K
    REVIEW OF THE ELECTRICAL COMMUNICATIONS LABORATORIES, 1976, 24 (5-6): : 383 - 389
  • [8] X. 25 LSI.
    Ito, Kiichiro
    Japan Annual Reviews in Electronics, Computers & Telecommunications, 1985, 20 : 315 - 325
  • [9] APPLICATION FOR SIT FOR LOGIC LSI.
    Mochida, Yasunori
    Nonaka, Terumoto
    Japan Annual Reviews in Electronics, Computers & Telecommunications, 1982, 1 : 249 - 257
  • [10] PERFORMANCE OF HETEROSTRUCTURE FET'S IN LSI.
    Tiwari, Sandip
    IEEE Transactions on Electron Devices, 1986, ED-33 (05) : 554 - 563