Efficient parallel VLSI architecture for matrix multiplication like algorithms

被引：0
|
作者：
Lafage, Anne
Jutand, Francis
机构：
来源：
International Workshop on Algorithms and Parallel VLSI Architectures | 1991年
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] Parallel Efficient Sparse Matrix-Matrix Multiplication on Multicore Platforms
    Patwary, Md. Mostofa Ali
    Satish, Nadathur Rajagopalan
    Sundaram, Narayanan
    Park, Jongsoo
    Anderson, Michael J.
    Vadlamudi, Satya Gautam
    Das, Dipankar
    Pudov, Sergey G.
    Pirogov, Vadim O.
    Dubey, Pradeep
    HIGH PERFORMANCE COMPUTING, ISC HIGH PERFORMANCE 2015, 2015, 9137 : 48 - 57
  • [22] EFFICIENT PARALLEL ALGORITHMS AND VLSI ARCHITECTURES FOR MANIPULATOR JACOBIAN COMPUTATION
    YEUNG, TB
    LEE, CSG
    IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS, 1989, 19 (05): : 1154 - 1166
  • [23] Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system
    Li, KQ
    Pan, Y
    Zheng, SQ
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 1998, 9 (08) : 705 - 720
  • [24] Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system
    State Univ of New York, New Paltz, United States
    IEEE Trans Parallel Distrib Syst, 8 (705-720):
  • [25] AN EFFICIENT AND SIMPLE VLSI TREE ARCHITECTURE FOR MOTION ESTIMATION ALGORITHMS
    JEHNG, YS
    CHEN, LG
    CHIUEH, TD
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1993, 41 (02) : 889 - 900
  • [26] An efficient VLSI architecture parallel prefix counting with domino logic
    Lin, R
    Nakano, K
    Olariu, S
    Zomaya, AY
    IPPS/SPDP 1999: 13TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM & 10TH SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING, PROCEEDINGS, 1999, : 273 - 277
  • [27] An energy-efficient parallel VLSI architecture for SVM classification
    Xu, Yin
    Chen, Zhijian
    Xiang, Xiaoyan
    Meng, Jianyi
    IEICE ELECTRONICS EXPRESS, 2018, 15 (07):
  • [28] A scalable highly parallel VLSI architecture dedicated to associative computing algorithms
    Layer, C
    Pfleiderer, HJ
    2005 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2005, : 418 - 421
  • [29] An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition
    Nandan, Durgesh
    Kanungo, Jitendra
    Mahajan, Anurag
    INTEGRATION-THE VLSI JOURNAL, 2017, 58 : 134 - 141
  • [30] VLSI SYSTEMS FOR BAND MATRIX MULTIPLICATION
    CHENG, KH
    SAHNI, S
    PARALLEL COMPUTING, 1987, 4 (03) : 239 - 258
12345