共 50 条
- [41] On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2761 - +
- [42] Simultaneous power fluctuation and average power minimization during nano-CMOS behavioral synthesis 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 577 - +
- [43] Distribution feeder reconfiguration for complex power loss minimization EEESD '07: PROCEEDINGS OF THE 3RD IASME/WSEAS INTERNATIONAL CONFERENCE ON ENERGY, ENVIRONMENT, ECOSYSTEMS AND SUSTAINABLE DEVELOPMENT, 2007, : 498 - 506
- [44] Why area might reduce power in nanoscale CMOS 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2329 - 2332
- [45] Low Power and Low Area CMOS Capacitance Multiplier CAS 2018 PROCEEDINGS: 2018 INTERNATIONAL SEMICONDUCTOR CONFERENCE, 2018, : 161 - 164
- [46] Finite state machine state assignment for area and power minimization 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 5303 - +
- [47] FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area 2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2018, : 256 - 259
- [48] Dynamic and short-circuit power of CMOS gates driving lossless transmission lines PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 39 - 44