Power and area minimization by reorganizing CMOS complex-gates

被引:0
|
作者
Toshiba Corp, Kawasaki-shi, Japan [1 ]
机构
来源
关键词
D O I
暂无
中图分类号
学科分类号
摘要
10
引用
收藏
相关论文
共 50 条
  • [21] Design and Simulation of Reliable Low Power CMOS Logic Gates
    Sharma, Vijay Kumar
    IETE JOURNAL OF RESEARCH, 2023, 69 (02) : 1022 - 1032
  • [22] Power dissipated by CMOS gates driving lossless transmission lines
    Ismail, YI
    Friedman, EG
    Neves, JL
    1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 1998, : 139 - 141
  • [23] Static power consumption in CMOS gates using independent bodies
    Guerrero, D.
    Millan, A.
    Juan, J.
    Bellido, M. J.
    Ruiz-de-Clavijo, P.
    Ostua, E.
    Viejo, J.
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2007, 4644 : 404 - +
  • [24] Single transistor primitive for timing and power modelling of CMOS gates
    Chatzigeorgiou, A
    Nikolaidis, S
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2000, 87 (10) : 1227 - 1238
  • [25] INPUT ORDERING FOR LOW-POWER IN CMOS LOGIC GATES
    PANWAR, R
    RENNELS, D
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1995, 78 (05) : 925 - 943
  • [26] Power and area minimization for multidimensional signal processing
    Markovic, Dejan
    Nikolic, Borivoje
    Brodersen, Robert W.
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (04) : 922 - 934
  • [27] Design of stuck-open fault testable CMOS complex gates
    Tsiatouhas, Y
    Haniotakis, T
    Halatsis, C
    Arapoyanni, A
    ELECTRONICS LETTERS, 1996, 32 (04) : 315 - 317
  • [28] Analytical input mapping for modelling energy dissipation of complex CMOS gates
    Di, J
    Yuan, JS
    Hagedorn, M
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2004, 151 (04): : 294 - 299
  • [29] CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff
    Lu, Yuanlin
    Agrawal, Vishwani D.
    JOURNAL OF LOW POWER ELECTRONICS, 2006, 2 (03) : 378 - 387
  • [30] Internal power dissipation modeling and minimization for submicronic CMOS design
    Maurine, P
    Rezzoug, M
    Auvergne, D
    INTEGRATED CIRCUIT DESIGN, PROCEEDINGS: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2000, 1918 : 129 - 138