共 50 条
- [41] A congestion-driven buffer planner with space reservation 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 5435 - +
- [42] X-Route: An X-architecture full-chip multilevel router 20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2007, : 229 - +
- [43] Novel full-chip gridless routing considering double-via insertion 43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 755 - +
- [44] A Full-Chip ESD Simulation Flow 2015 37TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2015,
- [46] Congestion-driven placement improvement using cell spreading 2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4: VOL 1: SIGNAL PROCESSING, 2006, : 2415 - 2419
- [48] Asynchronous parallel Genetic Algorithm for congestion-driven placement technique THIRD ACIS INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING RESEARCH, MANAGMENT AND APPLICATIONS, PROCEEDINGS, 2005, : 130 - 136
- [49] Full-chip verification of UDSM designs 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 453 - 460
- [50] Congestion-Driven Transmission Planning Considering the Impact of Generator Expansion 2008 IEEE POWER & ENERGY SOCIETY GENERAL MEETING, VOLS 1-11, 2008, : 4740 - 4740