An overview of on-chip compression architectures

被引：0
|
作者：
Cadence Design Systems, United States [1 ]
机构：
来源：
EDN | 2006年 / 18卷 / 61-68期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [31] Design space exploration for optimizing on-chip communication architectures
    Lahiri, K
    Raghunathan, A
    Dey, S
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (06) : 952 - 961
  • [32] Overview of On-Chip Performance Monitors for Clock Signals
    Huang, Shi-Yu
    2020 IEEE 29TH ASIAN TEST SYMPOSIUM (ATS), 2020, : 174 - 177
  • [33] An Efficient On-Chip Network with Packet Compression Capability
    Vafaiee, M.
    Jalili, M.
    Sabbaghi-Nadooshan, R.
    Sarbazi-Azad, H.
    2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2016, : 7 - 8
  • [34] An overview of achieving energy efficiency in on-chip networks
    Al Aziz, Masud
    Khan, Samee Ullah
    Loukopoulos, Thanasis
    Bouvry, Pascal
    Li, Hongxiang
    Li, Juan
    INTERNATIONAL JOURNAL OF COMMUNICATION NETWORKS AND DISTRIBUTED SYSTEMS, 2010, 5 (04) : 444 - 458
  • [35] Minimizing virtual channel buffer for routers in on-chip communication architectures
    Al Faruque, Mohammad Abdullah
    Henkel, Joerg
    2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1080 - 1085
  • [36] Scalar operand networks: On-chip interconnect for ILP in partitioned architectures
    Taylor, MB
    Lee, W
    Amarasinghe, S
    Agarwal, A
    NINTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 2003, : 341 - 353
  • [37] A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
    Zhu, Xinping
    Malik, Sharad
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2007, 12 (01)
  • [38] Simultaneous partitioning and frequency assignment for on-chip bus architectures.
    Srinivasan, S
    Li, L
    Vijaykrishnan, N
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 218 - 223
  • [39] On the Stability of Best Effort Flow Control Mechanisms in On-Chip Architectures
    Talebi, Mohammad S.
    Khonsari, Ahmad
    2008 IEEE INTERNATIONAL SYMPOSIUM ON MODELING, ANALYSIS & SIMULATION OF COMPUTER AND TELECOMMUNICATION SYSTEMS (MASCOTS), 2008, : 271 - 278
  • [40] Power analysis of system-level on-chip communication architectures
    Lahiri, K
    Raghunathan, A
    INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 236 - 241
12345