共 50 条
- [41] Fast exploration of bus-based on-chip communication architectures INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 242 - 247
- [42] Simulation-based approach for evaluating On-Chip Interconnect architectures 2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, 2008, : 75 - 80
- [43] On-Chip Photonic Interconnects for Scalable Multi-core Architectures 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, 2009, : 90 - 90
- [45] Cooperative communication based barrier synchronization in on-chip mesh architectures IEICE ELECTRONICS EXPRESS, 2011, 8 (22): : 1856 - 1862
- [46] A Survey on Performance of On-Chip Cache for Multi-core Architectures PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON INFORMATICS AND ANALYTICS (ICIA' 16), 2016,
- [47] Integrating on-chip temperature sensors into DfT schemes and BIST architectures 15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 440 - 445
- [48] Camellia: a Novel High Performance On-Chip Network for Multicore Architectures 2015 11TH INTERNATIONAL CONFERENCE ON SEMANTICS, KNOWLEDGE AND GRIDS (SKG), 2015, : 186 - 191
- [49] Token ring arbitration scheme for on-chip CDMA bus architectures MICROELECTRONICS JOURNAL, 2020, 106