An overview of on-chip compression architectures

被引:0
|
作者
Cadence Design Systems, United States [1 ]
机构
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [41] Fast exploration of bus-based on-chip communication architectures
    Pasricha, S
    Dutt, N
    Ben-Romdhane, M
    INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 242 - 247
  • [42] Simulation-based approach for evaluating On-Chip Interconnect architectures
    Suboh, Suboh
    Bakhouya, Mohamed
    Lopez-Buedo, Sergio
    El-Ghazawi, Tarek
    2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, 2008, : 75 - 80
  • [43] On-Chip Photonic Interconnects for Scalable Multi-core Architectures
    Kodi, Avinash Karanth
    Morris, Randy
    Louri, Ahmed
    Zhang, Xiang
    2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, 2009, : 90 - 90
  • [45] Cooperative communication based barrier synchronization in on-chip mesh architectures
    Chen, Xiaowen
    Lu, Zhonghai
    Jantsch, Axel
    Chen, Shuming
    Liu, Hai
    IEICE ELECTRONICS EXPRESS, 2011, 8 (22): : 1856 - 1862
  • [46] A Survey on Performance of On-Chip Cache for Multi-core Architectures
    Priya, B. Krishna
    Joshi, Amit D.
    Ramasubramanian, N.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON INFORMATICS AND ANALYTICS (ICIA' 16), 2016,
  • [47] Integrating on-chip temperature sensors into DfT schemes and BIST architectures
    Szekely, V
    Rencz, M
    Courtois, B
    15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 440 - 445
  • [48] Camellia: a Novel High Performance On-Chip Network for Multicore Architectures
    Chu, Slo-Li
    Shu, Sheng-Jie
    Chen, Ching-Chung
    Chen, Ching-Jung
    2015 11TH INTERNATIONAL CONFERENCE ON SEMANTICS, KNOWLEDGE AND GRIDS (SKG), 2015, : 186 - 191
  • [49] Token ring arbitration scheme for on-chip CDMA bus architectures
    Nikolic, Tatjana R.
    Djosic, Sandra M.
    Nikolic, Goran S.
    Djordjevic, Goran Lj
    MICROELECTRONICS JOURNAL, 2020, 106
  • [50] Design methodology for on-chip bus architectures using system-on-chip network protocol
    Lee, J.
    IET CIRCUITS DEVICES & SYSTEMS, 2012, 6 (02) : 85 - 94