A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores

被引：0
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作者：
Silva, Jorge Luiz E [1 ]
Lopes, Joelmir José [1 ]
机构：
[1] University of Sao Paulo, Department of Computer Systems, Av. Trabalhador Saocarlense, 400, Brazil
来源：
WSEAS Transactions on Computers | 2010年 / 9卷 / 05期
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页码：429 / 444
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