Component Dependencies Based Network-on-Chip Test

被引:1
|
作者
Huang, Letian [1 ]
Zhao, Tianjin [1 ,2 ]
Wang, Ziren [1 ,2 ]
Zhan, Junkai [1 ,3 ]
Wang, Junshi [1 ,3 ]
Wang, Xiaohang [4 ]
机构
[1] Univ Elect Sci & Technol China, Chengdu 610054, Peoples R China
[2] T Head Semicond Co Ltd, Chengdu 311121, Peoples R China
[3] Arm Technol China Co Ltd, Shanghai 200233, Peoples R China
[4] Zhejiang Univ, Hangzhou 310058, Peoples R China
关键词
Costs; Built-in self-test; Schedules; Routing; Computers; Vectors; Topology; Network-on-chip; reliability; online test; design-for-test;
D O I
10.1109/TC.2024.3457732
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
On-line test of NoC is essential for its reliability. This paper proposed an integral test solution for on-line test of NoC to reduce the test cost and improve the reliability of NOC. The test solution includes a new partitioning method, as well as a test method and a test schedule which are based on the proposed partitioning method. The new partitioning method partitions the NoC into a new type of basis unit under test (UUT) named as interdependent components based unit under test (iDC-UUT), which applies component test methods. The iDC-UUT have very low level of functional interdependency and simple physical connection, which results in small test overhead and high test coverage. The proposed test method consists of DFT architecture, test wrapper and test vectors, which can speed-up the test procedure and further improve the test coverage. The proposed test schedule reduces the blockage probability of data packets during testing by increasing the degree of test disorder, so as to further reduce the test cost. Experimental results show that the proposed test solution reduces power and area by 12.7% and 22.7% over an existing test solution. The average latency is reduced by 22.6% to 38.4% over the existing test solution.
引用
收藏
页码:2805 / 2816
页数:12
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