Simulation and Modelling for Network-on-Chip Based MPSoC

被引：0
|
作者：
Haase, Julian [1 ]
Goehringer, Diana [1 ,2 ]
机构：
[1] Tech Univ Dresden, Chair Adapt Dynam Syst, Dresden, Germany
[2] Tech Univ Dresden, Ctr Tactile Internet Human in the Loop CeTI, Dresden, Germany
来源：
APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2023 | 2023年 / 14251卷
关键词：
Simulator; Modelling; Network-on-Chip; SystemC TLM; heterogeneous MPSoC;
D O I：
10.1007/978-3-031-42921-7_26
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
As systems that can adapt their architecture and behavior in response to their environment become increasingly valuable in modern applications, research and development in inherently adaptive embedded systems is gaining momentum. Network-on-Chip based multi-processor architectures are promising for the development of adaptive embedded systems. The aim of this PhD work is to create a comprehensive simulation platform that bridges the gap between simulation and the design of such adaptive systems on real hardware. This paper introduces our proposed platform, presents preliminary results, and highlights upcoming steps and planned future work in this research topic.
引用
收藏
页码：366 / 370
页数：5
相关论文
共 50 条
  • [1] Secure Network-on-Chip Architectures for MPSoC: Overview and Challenges
    Daoud, Luka
    2018 IEEE 61ST INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2018, : 542 - 543
  • [2] MPEG-based performance comparison between network-on-chip and AMBA MPSoC
    Shafik, Rishad A.
    Rosinger, Paul
    Al-Hashimi, Bashir M.
    2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS, 2008, : 98 - 103
  • [3] Network-on-Chip based MPSoC architecture for k-mean clustering algorithm
    Khawaja, Sajid Gul
    Akram, M. Usman
    Khan, Shoab Ahmed
    Shaukat, Arslan
    Rehman, Saad
    MICROPROCESSORS AND MICROSYSTEMS, 2016, 46 : 1 - 10
  • [4] Multi-optical network-on-chip for large scale MPSoC
    Le Beux S.
    Trajkovic J.
    O'Connor I.
    Nicolescu G.
    Bois G.
    Paulin P.
    IEEE Embedded Systems Letters, 2010, 2 (03) : 77 - 80
  • [5] Traffic Characterization Based Stochastic Modelling of Network-on-Chip
    Adusumilli, Vijaya Bhaskar
    Tg, Venkatesh
    IEEE TRANSACTIONS ON COMPUTERS, 2023, 72 (04) : 1215 - 1222
  • [6] Modeling and Simulation of Network-on-Chip Routing Algorithm Based on OPNET
    Li, Fei
    Gao, Wanjia
    Chen, Liangchang
    Liu, Wenyi
    2020 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND HUMAN-COMPUTER INTERACTION (ICHCI 2020), 2020, : 323 - 327
  • [7] An Enhanced Network-on-Chip Simulation for Cluster-Based Routing
    Hassan, Ahmed S.
    Morgan, Ahmed A.
    El-Kharashi, M. Watheq
    11TH INTERNATIONAL CONFERENCE ON FUTURE NETWORKS AND COMMUNICATIONS (FNC 2016) / THE 13TH INTERNATIONAL CONFERENCE ON MOBILE SYSTEMS AND PERVASIVE COMPUTING (MOBISPC 2016) / AFFILIATED WORKSHOPS, 2016, 94 : 410 - 417
  • [8] Sampling-based Approaches to Accelerate Network-on-Chip Simulation
    Dai, Wenbo
    Jerger, Natalie Enright
    2014 EIGHTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2014, : 41 - 48
  • [9] xENoC - an experimental network-on-chip environment for parallel distributed computing on NoC-based MPSoC architectures
    Joven, Jaume
    Font-Bach, Oriol
    Castells-Rufas, David
    Martinez, Ricardo
    Teres, Lluis
    Carrabina, Jordi
    PROCEEDINGS OF THE 16TH EUROMICRO CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING, 2008, : 141 - +
  • [10] Heterogeneous modelling of an Optical Network-on-Chip with SystemC
    Brière, M
    Drouard, E
    Mieyeville, F
    Navarro, D
    O'Connor, I
    Gaffiot, F
    16TH INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS: SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE, 2005, : 10 - 16
12345