Test Time Reduction in Automated Test Equipment (ATE)-Based Mechanism of Network-on-Chip Communication Infrastructure

Network-on-chip (NoC) has been proposed as a scalable communication infrastructure to establish connections between integrated cores which are increased on a single chip. NoC structure consisting of components and elements such as routers, processing elements and links that can be error prone. Therefore, to achieve the correct functioning of a network, test operation has been a major concern for chip designers. In offline test mechanism, the distance between test pattern generator and destinations has significant impact on the test time. Using multicast scheme, this paper proposed a new mechanism that tests all cores. Our proposed approach first divides the network to four parts and then locates one ATE with four ports in the middle of the network. Based on our method, test operations are manipulated in parallel on each partition, individually. A new method is proposed that distributes test packets and collects test responses, simultaneously. Simulation results were also compared with some prior works by means of the proposed mechanism indicating that delivering test packets’ latency was decreased about 63% and the total number of hop counts to reach the specified destination was declined approximately 34%.