Ultrashallow junction formation using novel plasma doping technology beyond 50 nm MOS devices

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作者：

Nano Electronic Device Team, Future Technology Research Division, Electronics and Telecommunications Research Institute, 161, Gajeong-dong, Yuseong-gu, Daejon 305-360, Korea, Republic of ^{[1
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]}

不详 ^{[3
]}

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来源：

Jpn J Appl Phys Part 1 Regul Pap Short Note Rev Pap | / 4 B卷 / 2376-2379期

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Compendex;

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摘要：

Activation energy - Annealing - CMOS integrated circuits - Dielectric materials - Doping (additives) - Gates (transistor) - MOSFET devices - Plasma applications - Silicon on insulator technology - Silicon wafers

引用

共 48 条

[21] Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping
Walther, S
Lenoble, D
Lallernent, F
Grouillet, A
Erokhin, Y
Singh, V
Testoni, A
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION B-BEAM INTERACTIONS WITH MATERIALS AND ATOMS, 2005, 237 (1-2): : 126 - 130
[22] Simulation of surface engineering for ultra shallow junction formation of PMOS for the 90nm CMOS technology node and beyond
Bonnouvrier, J
Lenoble, D
Robilliart, E
Schwartzmann, T
Jaouen, H
2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2003, : 155 - 158
[23] Sub-50-nm physical gate length CMOS technology and beyond using steep halo
Wakabayashi, H
Ueki, M
Narihiro, M
Fukai, T
Ikezawa, N
Matsuda, T
Yoshida, K
Takeuchi, K
Ochiai, Y
Mogami, T
Kunio, T
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (01) : 89 - 95
[24] A robust SOISRAM architecture by using advanced ABC technology for 32 nm node and beyond LSTP devices
Hirano, Yuuichi
Tsujiuchi, Mikio
Ishikawa, Kozo
Shinohara, Hirofumi
Terada, Takashi
Maki, Yukio
Iwamatsu, Toshiaki
Eikyu, Katsumi
Uchida, Tetsuya
Obayashi, Shigeki
Nii, Koji
Tsukamoto, Yasumasa
Yabuuchi, Makoto
Ipposhi, Takashi
Oda, Hidekazu
Inoue, Yasuo
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 78 - +
[25] Shallow n+/p junction formation using PH3 plasma doping technique
Kim, Jeong Eun
Jung, Ho
Do, Seung Woo
Oh, Jae Geun
Hwang, Sun Hwan
Lee, Jin Ku
Ku, Ja Choon
Lee, Jong-Ho
Lee, Yong Hyun
Kong, Seong Ho
MICROPROCESSES AND NANOTECHNOLOGY 2007, DIGEST OF PAPERS, 2007, : 186 - 187
[26] Improvement of gate oxide reliability for tantalum-gate MOS devices using xenon plasma sputtering technology
Ushiki, T
Kawai, K
Yu, MC
Shinohara, T
Ino, K
Morita, M
Ohmi, T
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (11) : 2349 - 2354
[27] Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOICMOS
Kim, SD
Park, CM
Woo, JCS
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (10) : 1748 - 1754
[28] SUB-100 NM P+/N JUNCTION FORMATION USING PLASMA IMMERSION ION-IMPLANTATION
QIAN, XY
CHEUNG, NW
LIEBERMAN, MA
CURRENT, MI
CHU, PK
HARRINGTON, WL
MAGEE, CW
BOTNICK, EM
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION B-BEAM INTERACTIONS WITH MATERIALS AND ATOMS, 1991, 55 (1-4): : 821 - 825
[29] Damage-free cleaning of sub-50 nm devices using directed megasonics technology in a single wafer processor
Rosato, JJ
Yalamanchili, MR
Beck, MJ
Lillard, RY
ULTRA CLEAN PROCESSING OF SILICON SURFACES VII, 2005, 103-104 : 167 - 170
[30] The effects of C on the low-temperature formation and the properties of the spin-on dielectric films used for sub-50 nm technology and beyond
Lee, Wan-Gyu
THIN SOLID FILMS, 2012, 520 (07) : 3003 - 3008

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