Ultrashallow junction formation using novel plasma doping technology beyond 50 nm MOS devices

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作者：

Nano Electronic Device Team, Future Technology Research Division, Electronics and Telecommunications Research Institute, 161, Gajeong-dong, Yuseong-gu, Daejon 305-360, Korea, Republic of ^{[1
]}

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]}

不详 ^{[3
]}

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来源：

Jpn J Appl Phys Part 1 Regul Pap Short Note Rev Pap | / 4 B卷 / 2376-2379期

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Compendex;

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摘要：

Activation energy - Annealing - CMOS integrated circuits - Dielectric materials - Doping (additives) - Gates (transistor) - MOSFET devices - Plasma applications - Silicon on insulator technology - Silicon wafers

引用

共 48 条

[41] Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond
Choi, K.
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Yang, Q.
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Narayanan, V.
2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2009, : 138 - +
[42] Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond
Choi, K.
Jagannathan, H.
Choi, C.
Edge, L.
Ando, T.
Frank, M.
Jamison, P.
Wang, M.
Cartier, E.
Zafar, S.
Bruley, J.
Kerber, A.
Linder, B.
Callegari, A.
Yang, Q.
Brown, S.
Stathis, J.
Iacoponi, J.
Paruchuri, V.
Narayanan, V.
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : A138 - A139
[43] Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process
Choi, BY
Park, BG
Lee, YK
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2005 Symposium on VLSI Technology, Digest of Technical Papers, 2005, : 118 - 119
[44] Influence of hydrogen incorporation on the reliability of gate oxide formed by using low-temperature plasma selective oxidation applicable to sub-50-nm W-polymetal gate devices
Lim, Kwan-Yong
Sung, Min-Gyu
Cho, Heung-Jae
Kim, Yong Soo
Jang, Se-Aug
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Kim, Kwangok
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IEEE ELECTRON DEVICE LETTERS, 2008, 29 (04) : 338 - 340
[45] Development of PECVD processes for low-k (k≤2.5) and Cu barrier (k≤3.2) dielectric films using novel organosilanes as CVD precursors for 65nm technology node and beyond
Ashraf, A
Hwang, BK
Loboda, MJ
Schneider, R
Perz, S
ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004), 2004, : 387 - 391
[46] Novel contact-plug process with low-resistance nucleation layer using diborane-reduction tungsten atomic-layer-deposition method for 32 nm complementary metal-oxide-semiconductor devices and beyond
Yutani, Akie
Ichinose, Kazuhito
Maekawa, Kazuyoshi
Asai, Koyu
Kojima, Masayuki
JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (04) : 2464 - 2467
[47] Novel contact-plug process with low-resistance nucleation layer using diborane-reduction tungsten atomic-layer-deposition method for 32 nm complementary metal-oxide-semiconductor devices and beyond
Yutani, Akie
Ichinose, Kazuhito
Maekawa, Kazuyoshi
Asai, Koyu
Kojima, Masayuki
Japanese Journal of Applied Physics, 2008, 47 (4 PART 2): : 2464 - 2467
[48] Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.
Mathew, L
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Kalpat, S
Zavala, M
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Mora, R
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IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 731 - 734

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