SIMULTANEOUS SWITCHING GROUND NOISE CALCULATION FOR PACKAGED CMOS DEVICES

被引：114
|
作者：
SENTHINATHAN, R
PRINCE, JL
机构：
[1] Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 11期
关键词：
D O I：
10.1109/4.98995
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In the past, it was assumed that simultaneous switching noise created by CMOS outputs was directly proportional to the number of outputs switching simultaneously. Recent studies indicate that CMOS circuits exhibit sublinear behavior (due to the negative feedback influence) of power/ground noise (or bounce) as a function of the number of outputs switching simultaneously. Detailed electrical models, equations, and a trial architecture to calculate the switching noise are included. The results were compared to SPICE simulations and conventional power/ground noise calculations. The behavior of simultaneous switching noise as a function of constant-voltage (CV) device scaling is explained for small-geometry CMOS output drivers.
引用
收藏
页码：1724 / 1728
页数：5
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