Core logic simultaneous switching noise measurements on a 500MHz CMOS chip on a CBGA SCM

被引：2

作者：

Singh, B ^{[1
]}

Becker, WD ^{[1
]}

McAllister, M ^{[1
]}

机构：

[1] IBM Corp, Poughkeepsie, NY 12601 USA

来源：

48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/ECTC.1998.678757

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper the effect of on-chip thin oxide decoupling capacitors on power supply noise due to internal logic switching will be presented.The effect of logic switching on power supply noise as function of, amount of capacitance, capacitance placement, voltage, temperature and frequency of operation will be characterized. Results of both measurements and simulations will be presented.

引用

页码：605 / 609

页数：5

共 14 条

[1] A 500MHz 288kb CMOS SRAM macro for on-chip cache
Furumochi, K
Shimizu, H
Fujita, M
Akita, T
Izawa, T
Katsube, M
Aoyama, K
Kawamura, S
1996 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 1996, 39 : 156 - 157
[2] Simultaneous switching, noise, and reliability analyses of VLSI core logic
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[3] Estimation of on-chip simultaneous switching noise in VDSM CMOS circuits
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Audet, J
Kent, D
Libous, J
O'Connor, D
Rosser, S
Tremble, E
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Park, Joonsang
Kim, Haeyeon
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Toyoshima, H
Noda, K
Ohkubo, H
Uchida, T
Shimizu, T
Itani, T
Tokashiki, K
Kishimoto, K
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[9] Delay uncertainty due to on-chip simultaneous switching noise in high performance cmos integrated circuits
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[10] Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA
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