BORDER TRAPS IN MOS DEVICES

被引：305
|
作者：
FLEETWOOD, DM
机构：
[1] Sandia National Laboratories., Dept., NM, 87185–5800., 1332, Albuquerque
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1992年 / 39卷 / 02期
关键词：
D O I：
10.1109/23.277495
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
It is recommended that the terminology for oxide charges developed in 1979 by the Deal committee be updated to include near-interfacial oxide traps that communicate with the underlying Si and that these defects collectively be called "border traps." Justification for this nomenclature is presented and defining features of border traps are discussed. Border traps play an important role in determining low-frequency (1/f) noise levels in metal-oxide-semiconductor (MOS) transistors and also appear to have been observed in recent spin-dependent recombination studies on irradiated devices at microwave frequencies. This terminology is intended to add focus to discussions of defect type and location in MOS structures.
引用
收藏
页码：269 / 271
页数：3
相关论文
共 50 条
  • [31] Total-Ionizing-Dose Effects, Border Traps, and 1/f Noise in Emerging MOS Technologies
    Fleetwood, Daniel M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2020, 67 (07) : 1216 - 1240
  • [32] Extraction of interface and border traps in beyond-Si devices by accounting for generation and recombination in the semiconductor
    Sereni, Gabriele
    Larcher, Luca
    2015 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW), 2015, : 46 - 51
  • [33] NONEQUILIBRIUM RESPONSE OF MOS DEVICES TO A LINEAR VOLTAGE RAMP .1. BULK DISCRETE TRAPS
    BOARD, K
    SIMMONS, JG
    SOLID-STATE ELECTRONICS, 1977, 20 (10) : 859 - 867
  • [34] A Distributive-Transconductance Model for Border Traps in III-V/High-k MOS Capacitors
    Zhang, Chen
    Xu, Min
    Ye, Peide D.
    Li, Xiuling
    IEEE ELECTRON DEVICE LETTERS, 2013, 34 (06) : 735 - 737
  • [35] Response to comments to "A distributive-transconductance model for border traps in IIIAV/High-k MOS capacitors"
    Zhang, Chen
    Xu, Min
    Ye, Peide D.
    Li, Xiuling
    IEEE ELECTRON DEVICE LETTERS, 2013, 34 (11) : 1441 - 1441
  • [36] Effects of Interface Traps and Oxide Traps on Gate Capacitance of MOS Devices with Ultrathin (EOT ∼ 1 nm) High-κ Stacked Gate Dielectrics
    Sarwar, A. T. M. Golam
    Siddiqui, Mahmudur Rahman
    Siddique, Radwanul Hasan
    Khosru, Quazi Deen Mohd
    TENCON 2009 - 2009 IEEE REGION 10 CONFERENCE, VOLS 1-4, 2009, : 999 - 1003
  • [37] An equivalent capacitance model of oxide traps on frequency dispersion of C-V curve for MOS devices
    Lu, Han-Han
    Liu, Lu
    Xu, Jing-ping
    PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 103 - 105
  • [38] Interface and Border Traps in Ge pMOSFETs
    Fleetwood, D. M.
    Simoen, E.
    Francis, S. A.
    Zhang, C. X.
    Arora, R.
    Zhang, E. X.
    Schrimpf, R. D.
    Galloway, K. F.
    Mitard, J.
    Claeys, C.
    HIGH PURITY SILICON 12, 2012, 50 (05): : 189 - 203
  • [39] Modeling the Impact of Interface and Border Traps on Hysteresis in Encapsulated Monolayer MoS2 based Double Gated FETs
    Ghosh, Rittik
    Knobloch, Theresia
    Karl, Alexander
    Wilhelmer, Christoph
    Provias, Alexandros
    Waldhoer, Dominic
    Grasser, Tibor
    2024 AUSTROCHIP WORKSHOP ON MICROELECTRONICS, AUSTROCHIP 2024, 2024,
  • [40] Comments to A Distributive-Transconductance Model for Border Traps in III-V/High-[GRAPHICS] MOS Capacitors
    Taur, Yuan
    Chen, Han-Ping
    Yuan, Yu
    Yu, Bo
    IEEE ELECTRON DEVICE LETTERS, 2013, 34 (11) : 1439 - 1440
12345