A BUILT-IN SELF TEST TECHNIQUE FOR DIGITAL CIRCUITS

被引:0
|
作者
FASANG, PP
机构
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:65 / 68
页数:4
相关论文
共 50 条
  • [31] Enhanced technique for built-in self-test of sequential logic
    Chien, Benedict
    Simmons, Stan
    Canadian Conference on Electrical and Computer Engineering, 2004, 4 : 2009 - 2012
  • [32] A DATA-COMPRESSION TECHNIQUE FOR BUILT-IN SELF-TEST
    REDDY, SM
    SALUJA, KK
    KARPOVSKY, MG
    IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (09) : 1151 - 1156
  • [33] Built-in self-test
    Zorian, Yervant
    Microelectronic Engineering, 1999, 49 (01): : 135 - 138
  • [34] Built-in self-test
    Zorian, Y
    MICROELECTRONIC ENGINEERING, 1999, 49 (1-2) : 135 - 138
  • [35] A low power test pattern generation for built-in self-test based circuits
    Ye, Bo
    Li, Tianwang
    Zhao, Qian
    Zhou, Duo
    Wang, Xiaohua
    Luo, Min
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2011, 98 (03) : 301 - 309
  • [36] Design of digital circuits/systems with built-in testability
    Abbasi, SA
    Govil, A
    ICM 2002: 14TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2002, : 228 - 231
  • [37] Built-in self-test and self-calibration for analog and mixed signal circuits
    Chen, Tao
    Chen, Degang
    2019 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2019,
  • [38] A novel two-fold state skip logic Built-In Self-Test scheme for digital circuits
    Kavitha, Anbalagan
    SasiKumar, Subramanian
    COMPUTERS & ELECTRICAL ENGINEERING, 2015, 48 : 239 - 246
  • [39] A NEW BUILT-IN TEST SCHEME FOR DCVS CIRCUITS
    VASANTHAVADA, N
    KANOPOULOS, N
    1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 375 - 378
  • [40] Built-in test generation for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    1997 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1997, : 421 - 426