共 50 条
- [42] Layout Proximity Effects and Modeling Alternatives for IC Designs IEEE DESIGN & TEST OF COMPUTERS, 2010, 27 (02): : 18 - 18
- [44] Hierarchical design rule checking approach for IC layout Shanghai Jiaotong Daxue Xuebao, 1 (12-14, 18):
- [45] CHIPVIEW - IC LAYOUT EDITING ON A PERSONAL-COMPUTER IEEE CIRCUITS AND DEVICES MAGAZINE, 1989, 5 (02): : 47 - 49
- [46] Layout generation algorithm for CMOS analog IC cells UNIVERSITY AND INDUSTRY - PARTNERS IN SUCCESS, CONFERENCE PROCEEDINGS VOLS 1-2, 1998, : 653 - 656
- [47] DATA TRANSFER AND CHIP LAYOUT READY IC FOR PRODUCTION EDN MAGAZINE-ELECTRICAL DESIGN NEWS, 1984, 29 (09): : 280 - &
- [48] Constraints space management for the layout of analog IC's DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 971 - 972
- [49] Lossless compression algorithm for hierarchical IC layout data OPTICAL MICROLITHOGRAPHY XX, PTS 1-3, 2007, 6520