共 50 条
- [41] Influence of Electroplating Current Density on Through Silicon Via Filling 2015 16TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, 2015,
- [42] Formation of Sn Through-Silicon-Via and Its Interconnection Process for Chip Stack Packages KOREAN JOURNAL OF METALS AND MATERIALS, 2010, 48 (06): : 557 - 564
- [44] Effects of JGB and PEG on Through Silicon Via Filling Process ICEPT2019: THE 2019 20TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, 2019,
- [47] Understanding Effect of Additives in Copper Electroplating Filling for Through Silicon Via 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 251 - 253
- [48] Influence of Leveler Concentration on Copper Electrodeposition for Through Silicon Via Filling 2009 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2009), 2009, : 780 - +
- [49] Development of Fast Filling Acid Copper Plating for through Silicon via 2024 International Conference on Electronics Packaging, ICEP 2024, 2024, : 227 - 228
- [50] A Rigorous Approach for the Modeling of Through-Silicon-Via Pairs Using Multipole Expansions IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (01): : 117 - 125