Area and Energy-Efficient 4-2 Compressor Design for Tree Multiplier Implementation

Redundant gates of 4-2 compressor (hereafter, it is referred as 42C) has been removed by simplification of compressor output Boolean expression, that results in power consumption minimization. Further, the proposed design is implemented in full swing gate diffusion input logic, a low-power design technique with minimum transistor count. To evaluate the performance of existing and proposed compressor designs, they are simulated using SPICE simulation at 45 nm technology model. Also, the area is calculated from their corresponding generated layouts for the same technology model. From the simulation results, it is observed that the proposed compressor has shown performance improvement in terms of power delay product by 45% than the recently reported compressor. Further, to study the performance of proposed compressor in an application environment, a 16-bit multiplier is implemented. Its simulation results confirmed that the performance improvement is consistent in the multiplier too.