Delay Test Generation: A Hardware Perspective

被引：0
|
作者：
Jacob Savir
机构：
[1] New Jersey Institute of Technology,ECE Dept.
来源：
Journal of Electronic Testing | 1997年 / 10卷
关键词：
delay test; linear feedback shift register; cellular automata; transition test; skewed-load delay test; shift dependency; pseudo-random test;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
An important problem one faces during design of a built-in self-test(BIST) based delay test is the selection of a proper generator toapply the test vectors. This problem is due to the need of applyinga pair of patterns to detect any given delay fault. The secondvector has to be launched against the logic immediately following thefirst vector. This timing requirement places severe restrictions onthe kind of hardware suitable for the task, especially in built-inself-test applications where the generator must reside on chip.
引用
收藏
页码：245 / 254
页数：9
相关论文
共 50 条
  • [41] Timing verification and delay test generation for hierarchical designs
    Krishnamachary, A
    Abraham, JA
    Tupuri, RS
    VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2001, : 157 - 162
  • [42] A TEST-GENERATION SYSTEM FOR PATH DELAY FAULTS
    PATIL, S
    REDDY, SM
    PROCEEDINGS - IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS & PROCESSORS, 1989, : 40 - 43
  • [43] Test Generation for Open and Delay Faults in CMOS Circuits
    Wu, Cheng-Hung
    Lee, Kuen-Jong
    Reddy, Sudhakar M.
    2017 INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA), 2017, : 21 - 26
  • [44] Diagnostic Test Generation for Small Delay Defect Diagnosis
    Guo, Ruifeng
    Cheng, Wu-Tung
    Kobayashi, Takeo
    Tsai, Kun-Han
    2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 224 - 227
  • [45] Efficient path delay test generation for custom designs
    Kang, SH
    Underwood, B
    Law, WO
    Konuk, H
    ETRI JOURNAL, 2001, 23 (03) : 138 - 149
  • [46] Path Unselection for Path Delay Fault Test Generation
    Pomeranz, Irith
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (02) : 267 - 275
  • [47] Efficient path delay test generation based on stuck-at test generation using checker circuitry
    Iwagaki, Tsuyoshi
    Ohtake, Satoshi
    Kaneko, Mineo
    Fujiwara, Hideo
    IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 418 - +
  • [48] A method of test generation for path delay faults using stuck-at fault test generation algorithms
    Ohtake, S
    Ohtani, K
    Fujiwara, H
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 310 - 315
  • [49] Application of Preselection of Test Subsequences in Sequential Test Generation for Functional Delay Faults
    Bareisa, E.
    Jusas, V.
    Motiejunas, K.
    Seinauskas, R.
    Motiejunas, L.
    ELEKTRONIKA IR ELEKTROTECHNIKA, 2012, 118 (02) : 33 - 37
  • [50] Hybrid delay scan: A low hardware overhead scan-based delay test technique for high fault coverage and compact test sets
    Wang, S
    Liu, X
    Chakradhar, ST
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1296 - 1301
12345