共 50 条
- [1] Low overhead partial enhanced scan technique for compact and high fault coverage transition delay test patterns PROCEEDINGS OF THE 13TH IEEE EUROPEAN TEST SYMPOSIUM: ETS 2008, 2008, : 125 - 130
- [2] Improving transition delay fault coverage using hybrid scan-based technique DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, 2005, : 187 - 195
- [5] A scan-based delay test method for reduction of overtesting DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 521 - 526
- [7] A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS, 2003, : 574 - 583
- [9] Delay test scan flip-flop: DFT for high coverage delay testing 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 763 - +
- [10] Low-power technique of scan-based design for test ELECTRONICS LETTERS, 2000, 36 (23) : 1920 - 1921