Hardware Implementation of a High-Speed Adaptive Filter Using a Combination of Systolic and Convex Architectures

In this paper, an improved high-speed adaptive filter is proposed and implemented using a field-programmable gate array platform. Specifically, a new filter structure combining systolic and convex architectures has been analyzed and compared with conventional filter architectures. The new filter structure efficiently removes power line interference noise from electrocardiogram signals at high convergence speeds. The systolic architecture is used to improve the convergence speed of the filter, and the convex architecture is used in combination to improve the signal-to-noise ratio of the filter. One fast filter was designed using the retimed delay recursive least square algorithm (recursive least square filter design with systolic architecture), and it was combined with one slow filter designed using the least mean square algorithm based on convex combination architecture. The proposed filter architectures are assessed for electrocardiogram noise cancellation, obtained from the MIT-BIH database, and the performance is compared with various filter structures in terms of the signal-to-noise ratio, convergence speed, learning behaviors, and complexity. The results show an improvement in signal-to-noise ratio of 24.2% and an increase in convergence speed of 50% when compared with conventional filter structures.