Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs-Part I: Drain Current and Transconductances

被引:7
|
作者
Makris, Nikolaos [1 ]
Jazaeri, Farzan [2 ]
Sallese, Jean-Michel [2 ]
Sharma, Rupendra Kumar [3 ]
Bucher, Matthias [1 ]
机构
[1] Tech Univ Crete, Sch Elect & Comp Engn, Khania 73100, Greece
[2] Ecole Polytech Fed Lausanne, Sch Engn, CH-1015 Lausanne, Switzerland
[3] Czech Tech Univ, Dept Microelect, Prague 16627, Czech Republic
基金
瑞士国家科学基金会;
关键词
Analytical model; circuit simulation; compact model; junction field-effect transistor (JFET); temperature effect; FIELD-EFFECT TRANSISTORS; CIRCUIT SIMULATION; JFET; MOSFETS; VOLTAGE;
D O I
10.1109/TED.2018.2838101
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.
引用
收藏
页码:2744 / 2750
页数:7
相关论文
共 47 条
  • [31] A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor
    Ratul Kumar Baruah
    Roy P. Paily
    Journal of Computational Electronics, 2016, 15 : 45 - 52
  • [32] Quantum short-channel compact modeling of drain-current in double-gate MOSFET
    Munteanu, D
    Autran, JL
    Loussier, X
    Harrison, S
    Cerutti, R
    Skotnicki, T
    PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, : 137 - 140
  • [33] ANALYTICAL MODELING OF DRAIN CURRENT, CAPACITANCE AND TRANSCONDUCTANCE IN SYMMETRIC DOUBLE-GATE MOSFETs CONSIDERING QUANTUM EFFECTS
    Palanichamy, Vimala
    Balamurugan, N. B.
    INTERNATIONAL JOURNAL OF NANOSCIENCE, 2013, 12 (01)
  • [34] Charge-based model for long-channel cylindrical surrounding-gate MOSFETs from intrinsic channel to heavily doped body
    Liu, Feng
    He, Jin
    Zhang, Lining
    Zhang, Jian
    Hu, Jinghua
    Ma, Chenyue
    Chan, Mansun
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (08) : 2187 - 2194
  • [35] A carrier-based approach for compact modeling of the long-channel-undoped symmetric double-gate MOSFETs
    He, Jin
    Liu, Feng
    Zhang, Jian
    Feng, Jie
    Hu, Jinhua
    Yang, Shengqi
    Chan, Mansun
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (05) : 1203 - 1209
  • [36] A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation
    Lime, F.
    Ritzenthaler, R.
    Ricoma, M.
    Martinez, F.
    Pascal, F.
    Miranda, E.
    Faynot, O.
    Iniguez, B.
    SOLID-STATE ELECTRONICS, 2011, 57 (01) : 61 - 66
  • [37] CURRENT/VOLTAGE CHARACTERISTICS OF THE SHORT-CHANNEL DOUBLE-GATE TRANSISTOR. PART I
    Cumberbatch, Ellis
    Smith, Stefan G. Llewellyn
    SIAM JOURNAL ON APPLIED MATHEMATICS, 2018, 78 (02) : 877 - 896
  • [38] An analytical charge-based drain current model for nano-scale In0.52Al0.48As-In0.53Ga0.47 as a separated double-gate HEMT
    Rathi, Servin
    Jogi, Jyotika
    Gupta, Mridula
    Gupta, R. S.
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2010, 25 (11)
  • [39] Charge-based Modeling of Channel Material-Engineered P-type Double Gate MOSFET
    Kumari, Vandana
    Ilango, Aravindan
    Saxena, Manoj
    Gupta, Mridula
    2014 IEEE 2ND INTERNATIONAL CONFERENCE ON EMERGING ELECTRONICS (ICEE), 2014,
  • [40] Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor
    Gaidhane, Amol D.
    Pahwa, Girish
    Verma, Amit
    Chauhan, Yogesh Singh
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (05) : 2024 - 2032