VLSI implementation of efficient coder for deep space communication

被引:0
|
作者
Sofia, Jane J. [1 ]
Jayakumari, J. [1 ]
机构
[1] Noorul Islam Ctr Higher Educ, Dept Elect & Commun Engn, Thuckalay, Tamil Nadu, India
关键词
deep space communication; LT code;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
With the advent of the space age, deep space exploration increasingly has become an important strategic task for human beings. To carry out space exploration, it is necessary to launch many space detectors with a variety of purposes, so that it requires establishing effective communication between the detector, and between the detectors and the Earth, that is to carry out deep space communication. Deep space exploration has proven that deep space communication monitoring and controlling network plays an important role in the development of space. Its basic characteristic is that it involves a very large distance, and is more difficult comparing with other means of communication. Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work deals with the design, simulation and implementation of an efficient channel coder for deep space communication. In this paper, it is proposed to implement the channel encoder using LT coder. A significant characteristic of the LT code is rateless. It can be said that the code words create and launch ceaselessly like the fountain, until enough codes are received to restore raw data. Deep Space communications channel has a more abundant frequency bandwidth, allowing the use of encoding with lower frequency band utilization ratio and binary modulation method. Fountain code is a sparse matrix coding based on erasure channel. The system is realized using FPGA.
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页数:6
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