FPGA digital down converter IP for SDR terminals

被引：0

作者：

Girau, G ^{[1
]}

Martina, M ^{[1
]}

Molino, A ^{[1
]}

Terreno, A ^{[1
]}

Vacca, F ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Elettron, CERCOM Ctr Multimedia Radio Commun, I-10129 Turin, Italy

来源：

THIRTY-SIXTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS - CONFERENCE RECORD, VOLS 1 AND 2, CONFERENCE RECORD | 2002年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

During the past years, software platforms have proved a superior scalability with respect to hardware solutions. However, wireless communication rates can not be faced resorting only to software. Software Defined Radio paradigm will try to push reconfigurable blocks as near as possible to the antenna. The first block suitable in this implementation is the Digital Down Converter, needed to adapt higher antenna's data rate to Intermediate Frequency ones. In this paper a fully reconfigurable IP of a CIC filter; an economical class of multiplier-less filters, is proposed. FPGA implementation has lead to very satisfactory results: 135 MHz on a XCV100E.

引用

页码：1010 / 1014

页数：5

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