Optimally Approximated and Unbiased Floating-Point Multiplier with Runtime Configurability

被引:0
|
作者
Chen, Chuangtao [2 ]
Yang, Sen [1 ]
Qian, Weikang [4 ]
Imani, Mohsen [5 ]
Yin, Xunzhao [1 ]
Zhuo, Cheng [1 ,3 ]
机构
[1] Zhejiang Univ, Coll Informat Sci & Elect Engn, Hangzhou, Peoples R China
[2] Zhejiang Univ, Coll Elect Engn, Hangzhou, Peoples R China
[3] Fudan Univ, Sch Microelect, ASIC & Syst Key Lab, Shanghai, Peoples R China
[4] Shanghai Jiao Tong Univ, Univ Michigan Shanghai Jiao Tong Univ Joint Inst, Shanghai, Peoples R China
[5] Univ Calif Irvine, Dept Comp Sci & Engn, Irvine, CA USA
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Approximate computing is a promising alternative to improve energy efficiency for IoT devices on the edge. This work proposes an optimally approximated and unbiased floating-point approximate multiplier with runtime configurability. We provide a theoretically sound formulation that turns multiplication approximation to an optimization problem. With the formulation and findings, a multilevel architecture is proposed to easily incorporate runtime configurability and module execution parallelism. Finally, an optimization scheme is applied to improve the area, making it linearly dependent on the precision, instead of quadratically or exponentially as in prior work. In addition to the optimal approximation and configurability, the proposed design has an efficient circuit implementation that uses inversion, shift and addition instead of complex arithmetic operations. When compared to the prior state-of-the-art approximate floating-point multiplier, ApproxLP [30], the proposed design outperforms in all aspects including accuracy, area, and delay. By replacing the regular full-precision multiplier in GPU, the proposed design can improve the energy efficiency for various edge computing tasks. Even with Level 1 approximation, the proposed design improves energy efficiency up to 122x for machine learning on C1FAR-10, with almost negligible accuracy loss.
引用
收藏
页数:9
相关论文
共 50 条
  • [21] A tool for unbiased comparison between logarithmic and floating-point arithmetic
    Detrey, Jeremie
    De Dinechin, Florent
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2007, 49 (01): : 161 - 175
  • [22] A quadruple precision and dual double precision floating-point multiplier
    Akkas, A
    Schulte, MJ
    EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2003, : 76 - 81
  • [23] CFPM: Run-time Configurable Floating-Point Multiplier
    Saggese, Gerardo
    Napoli, Ettore
    Strollo, Antonio Giuseppe Maria
    2023 18TH CONFERENCE ON PH.D RESEARCH IN MICROELECTRONICS AND ELECTRONICS, PRIME, 2023, : 173 - 176
  • [24] Decimal Floating-Point Multiplier With Binary-Decimal Compression Based Fixed-Point Multiplier
    Gao, Shuli
    Al-Khalili, Dhamin
    Langlois, J. M. Pierre
    Chabini, Noureddine
    2017 IEEE 30TH CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE), 2017,
  • [25] Software Acceleration of Floating-point Multiplication using Runtime Code Generation
    Aracil, Charles
    Courousse, Damien
    2013 4TH ANNUAL INTERNATIONAL CONFERENCE ON ENERGY AWARE COMPUTING SYSTEMS AND APPLICATIONS (ICEAC), 2013, : 18 - 23
  • [26] Dual-mode floating-point multiplier architectures with parallel operations
    Akkas, Ahmet
    Schulte, Michael J.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2006, 52 (10) : 549 - 562
  • [27] FLOATING-POINT CELLULAR-LOGIC MULTIPLIER WITH VARIABLE DYNAMIC RANGE
    EDWARDS, CR
    ELECTRONICS LETTERS, 1971, 7 (25) : 747 - &
  • [28] A single/double precision floating-point multiplier design for multimedia applications
    Mersin University, Engineering Faculty, Department of Computer Science, 33342, Mersin, Turkey
    不详
    Istanb. Univ. J. Electr. Electron. Eng., 2009, 1 (827-831):
  • [29] A Parallel IEEE P754 Decimal Floating-Point Multiplier
    Hickmann, Brian
    Krioukov, Andrew
    Schulte, Michael
    Erle, Mark
    2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, : 296 - +
  • [30] Low power single precision BCD floating-point Vedic multiplier
    Ramya, V.
    Seshasayanan, R.
    MICROPROCESSORS AND MICROSYSTEMS, 2020, 72