Open-Source RISC-V Processor IP Cores for FPGAs - Overview and Evaluation

被引:0
|
作者
Hoeller, Roland [1 ]
Haselberger, Dominic [1 ]
Ballek, Dominik [1 ]
Roessler, Peter [1 ]
Krapfenbauer, Markus [2 ]
Linauer, Martin [2 ]
机构
[1] Univ Appl Sci Technikum Wien, Dept Elect Engn, Hochstadtpl 6, A-1200 Vienna, Austria
[2] Kapsch TrafficCom AG, Europl 2, A-1120 Vienna, Austria
关键词
Field Programmable Gate Arrays; Programmable System-on-Chip; Open-Source CPU Cores; RISC-V; IP Core;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Advances in semiconductor miniaturization are an important driver for Field Programmable Gate Arrays (FPGAs) since their invention in the 1980s. The increasing number of available on chip logic resources on one hand and on the other hand a decrease in part costs let the FPGA market grow steadily in recent years. It comes thus at no surprise that more and more microprocessors are integrated into programmable logic devices as they represent the central functionality in many digital systems. In parallel to these technological developments the open-source hardware community grew steadily in the last two decades. More than hundred open-source CPU cores can thus be found and selecting a core for a design project has to be done with care. In this work we thus want to focus on open-source 32-bit CPU IP cores suitable for FPGAs and which support the upcoming free and open RISC-V instruction set architecture that has some interesting advantages when compared to commercial CPU cores (as will be outlined in the paper). An overview on available projects and activities will be given and evaluation results for a selection of cores will be presented.
引用
收藏
页码:122 / 127
页数:6
相关论文
共 50 条
  • [21] An Academic RISC-V Silicon Implementation Based on Open-Source Components
    Abella, Jaume
    Bulla, Calvin
    Cabo, Guillem
    Cazorla, Francisco J.
    Cristal, Adrian
    Doblas, Max
    Figueras, Roger
    Gonzalez, Alberto
    Hernandez, Carles
    Hernandez, Cesar
    Jimenez, Victor
    Kosmidis, Leonidas
    Kostalabros, Vatistas
    Langarita, Ruben
    Leyva, Neiel
    Lopez-Paradis, Guillem
    Marimon, Joan
    Martinez, Ricardo
    Mendoza, Jonnatan
    Moll, Francesc
    Moreto, Miquel
    Pavon, Julian
    Ramirez, Cristobal
    Ramirez, Marco A.
    Rojas, Carlos
    Rubio, Antonio
    Ruiz, Abraham
    Sonmez, Nehir
    Soria, Victor
    Teres, Lluis
    Unsal, Osman
    Valero, Mateo
    Vargas, Ivan
    Villa, Luis
    2020 XXXV CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS), 2020,
  • [22] PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability
    Mallasen, David
    Murillo, Raul
    Del Barrio, Alberto A.
    Botella, Guillermo
    Pinuel, Luis
    Prieto-Matias, Manuel
    IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 2022, 10 (03) : 1241 - 1252
  • [23] HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores
    Fuguet, Cesar
    PROCEEDINGS OF THE 20TH ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS 2023, CF 2023, 2023, : 377 - 378
  • [24] X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller
    Schiavone, Pasquale Davide
    Machetti, Simone
    Peon-Quiros, Miguel
    Miranda, Jose
    Denkinger, Benoit
    Muller, Thomas Christoph
    Rodriguez, Ruben
    Nasturzio, Saverio
    Alonso, David Atienza
    PROCEEDINGS OF THE 20TH ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS 2023, CF 2023, 2023, : 379 - 380
  • [25] Open-source processor route for Lattice FPGAs
    IET Electronics Systems and Software, 2006, 4 (05): : 46 - 47
  • [26] RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor
    Kanamori, Takuto
    Odan, Takashi
    Hirohata, Kazuki
    Kise, Kenji
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2022, E105D (12) : 1999 - 2007
  • [27] Poster: Marian: An Open Source RISC-V Processor with Zvk Vector Cryptography Extensions
    Szymkowiak, Thomas
    Isufi, Endrit
    Saarinen, Markku-Juhani
    PROCEEDINGS OF THE 2024 ACM SIGSAC CONFERENCE ON COMPUTER AND COMMUNICATIONS SECURITY, CCS 2024, 2024, : 4931 - 4933
  • [28] SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors
    Damian, Mihaela
    Oppermann, Julian
    Spang, Christoph
    Koch, Andreas
    PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, 2022, : 169 - 174
  • [29] Developing a Multicore Platform Utilizing Open RISC-V Cores
    Jang, Hyeonguk
    Han, Kyuseung
    Lee, Sukho
    Lee, Jae-Jin
    Lee, Seung-Yeong
    Lee, Jae-Hyoung
    Lee, Woojoo
    IEEE ACCESS, 2021, 9 : 120010 - 120023
  • [30] Towards a metrics suite for evaluating cache side-channel vulnerability: Case studies on an open-source RISC-V processor
    Guo, Pengfei
    Yan, Yingjian
    Wang, Junjie
    Zhong, Jingxin
    Liu, Yanjiang
    Xu, Jinsong
    COMPUTERS & SECURITY, 2023, 135