An infrastructure IP for on-chip clock jitter measurement

被引：0

作者：

Huang, JJ ^{[1
]}

Huang, JL ^{[1
]}

机构：

[1] Ind Technol Res Inst, SoC Technol Ctr, Hsinchu, Taiwan

来源：

IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two different delay values and the probabilities it leads the two delayed versions are measured. The RMS period jitter value can then be derived from the probabilities and the delay difference. Both behavior and circuit simulations are performed to validate the proposed technique and analyze the design tradeoffs, and a prototype chip has been designed for further validation.

引用

页码：186 / 191

页数：6

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