An infrastructure IP for on-chip clock jitter measurement

被引：0

作者：

Huang, JJ ^{[1
]}

Huang, JL ^{[1
]}

机构：

[1] Ind Technol Res Inst, SoC Technol Ctr, Hsinchu, Taiwan

来源：

IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two different delay values and the probabilities it leads the two delayed versions are measured. The RMS period jitter value can then be derived from the probabilities and the delay difference. Both behavior and circuit simulations are performed to validate the proposed technique and analyze the design tradeoffs, and a prototype chip has been designed for further validation.

引用

页码：186 / 191

页数：6

共 50 条

[21] On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs
Liang, Joshua
Jalali, Mohammad Sadegh
Sheikholeslami, Ali
Kibune, Masaya
Tamura, Hirotaka
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (04) : 845 - 855
[22] Jitter suppressed on-chip clock distribution using package plane cavity resonance
Lee, Woojin
Ryu, Chunghyun
Park, Jongbae
Kim, Joungho
2008 ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND 19TH INTERNATIONAL ZURICH SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1 AND 2, 2008, : 427 - 430
[23] An on-chip jitter measurement circuit with sub-picosecond resolution
Jenkins, KA
Jose, AP
Heidel, DF
ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2005, : 157 - 160
[24] On-chip accumulated jitter measurement for phase-locked loops
Li, Chih-Feng
Yang, Shao-Sheng
Chang, Tsin-Yuan
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 1184 - 1187
[25] On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs
Kim, Jaeha
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2009, 56 (06) : 449 - 453
[26] On-Chip Jitter Learning for PLL
Chen, Wei-Hao
Huang, Shi-Yu
IEEE DESIGN & TEST, 2022, 39 (04) : 58 - 63
[27] On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR
Son, Kyung-Sub
Kang, Jin-Ku
IEICE ELECTRONICS EXPRESS, 2015, 12 (15):
[28] On-chip calibration technique for delay line based bist jitter measurement
Nelson, B
Soma, M
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2004, : 944 - 947
[29] On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR
Liang, Joshua
Sheikholeslami, Ali
Tamura, Hirotaka
Yamaguchi, Hisakatsu
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (03) : 750 - 761
[30] A scalable on-chip jitter extraction technique
Ong, CK
Hong, DW
Cheng, KT
Wang, LC
22ND IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2004, : 267 - 272

← 1 2 3 4 5 →