An infrastructure IP for on-chip clock jitter measurement

被引：0
|
作者：
Huang, JJ [1 ]
Huang, JL [1 ]
机构：
[1] Ind Technol Res Inst, SoC Technol Ctr, Hsinchu, Taiwan
来源：
IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two different delay values and the probabilities it leads the two delayed versions are measured. The RMS period jitter value can then be derived from the probabilities and the delay difference. Both behavior and circuit simulations are performed to validate the proposed technique and analyze the design tradeoffs, and a prototype chip has been designed for further validation.
引用
收藏
页码：186 / 191
页数：6
相关论文
共 50 条
  • [1] On-chip Reference-less Clock Jitter Measurement
    Bal, Ankur
    Singh, Rupesh
    2018 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS 2018), 2018,
  • [2] Low-Cost On-Chip Clock Jitter Measurement Scheme
    Omana, Martin
    Rossi, Daniele
    Giaffreda, Daniele
    Metra, Cecilia
    Mak, T. M.
    Rahman, Asifur
    Tam, Simon
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (03) : 435 - 443
  • [3] Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors
    Metra, C.
    Omana, M.
    Mak, T. M.
    Rahman, A.
    Tam, S.
    23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2008, : 465 - +
  • [4] Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling
    Lyu, Yinxuan
    Feng, Jianhua
    Zhu, Kai
    Ye, Hongfei
    Yu, Dunshan
    MICROELECTRONICS JOURNAL, 2020, 96
  • [5] An on-chip jitter measurement circuit for the PLL
    Tsai, CC
    Lee, CL
    ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2003, : 332 - 335
  • [6] On-chip jitter measurement for phase locked loops
    Xia, T
    Lo, JC
    17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, : 399 - 407
  • [7] An on-chip delta-time-to-voltage converter for real-time measurement of clock jitter
    Ichiyama, Kiyotaka
    Ishida, Masahiro
    Yamaguchi, Takahiro J.
    Soma, Mani
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2798 - +
  • [8] On-chip Jitter and Oscilloscope Circuits Using an Asynchronous Sample Clock
    Schaub, J. D.
    Gebara, F. H.
    Nguyen, T. Y.
    Vo, I.
    Pena, J.
    Acharyya, D. J.
    ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 126 - 129
  • [9] Low-jitter on-chip clock for RSFQ circuit applications
    Zhang, Y
    Gupta, D
    SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 1999, 12 (11): : 769 - 772
  • [10] Low-jitter on-chip clock for RSFQ circuit applications
    Zhang, Yongming
    Gupta, Deepnarayan
    Superconductor Science and Technology, 1999, 12 (11): : 769 - 772
12345