3-D Modeling of Fringing Gate Capacitance in Gate-all-around Cylindrical Silicon Nanowire MOSFETs

被引：0
|
作者：
An, TaeYoon [1 ]
Kim, SoYoung [1 ]
机构：
[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon, Gyeonggi Do, South Korea
来源：
2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013) | 2013年
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance C-side; parallel capacitance C-gsd; perpendicular capacitance C-gex. Each capacitance is calculated using the following methods: conformal mapping, integral and non-dimensionalization. The proposed model is verified with a three-dimensional field solver, Raphael. Based on the proposed model, the fringing capacitance can be easily predicted in the vertically and horizontally stacked multi-wire SNWTs.
引用
收藏
页码：256 / 259
页数：4
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