3-D Modeling of Fringing Gate Capacitance in Gate-all-around Cylindrical Silicon Nanowire MOSFETs

被引:0
|
作者
An, TaeYoon [1 ]
Kim, SoYoung [1 ]
机构
[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon, Gyeonggi Do, South Korea
来源
2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013) | 2013年
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance C-side; parallel capacitance C-gsd; perpendicular capacitance C-gex. Each capacitance is calculated using the following methods: conformal mapping, integral and non-dimensionalization. The proposed model is verified with a three-dimensional field solver, Raphael. Based on the proposed model, the fringing capacitance can be easily predicted in the vertically and horizontally stacked multi-wire SNWTs.
引用
收藏
页码:256 / 259
页数:4
相关论文
共 50 条
  • [41] Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors
    Xiaoqiao DONG
    Ming LI
    Wanrong ZHANG
    Yuancheng YANG
    Gong CHEN
    Shuang SUN
    Jianing WANG
    Xiaoyan XU
    Xia AN
    Science China(Information Sciences), 2020, 63 (10) : 288 - 290
  • [42] Analytical Modeling of Gate Capacitance and Drain Current of Gate-all-around InxGa1-xAs Nanowire MOSFET
    Khan, Saeed Uz Zaman
    Hossain, Md. Shafayat
    Hossen, Md. Obaidul
    Rahman, Fahim Ur
    Zaman, Rifat
    Khosru, Quazi D. M.
    2014 2ND INTERNATIONAL CONFERENCE ON ELECTRONIC DESIGN (ICED), 2014, : 89 - 93
  • [43] Compact Modeling of Schottky Gate-all-around Silicon Nanowire Transistors with Halo Doping
    Mishra, Girish Shankar
    Mohankumar, N.
    Mahesh, V.
    Vamsidhar, Y.
    Kumar, M. Arun
    SILICON, 2022, 14 (04) : 1455 - 1462
  • [44] Compact Modeling of Schottky Gate-all-around Silicon Nanowire Transistors with Halo Doping
    Girish Shankar Mishra
    N. Mohankumar
    V. Mahesh
    Y. Vamsidhar
    M. Arun Kumar
    Silicon, 2022, 14 : 1455 - 1462
  • [45] Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET
    Kushwaha, Pragya
    Agarwal, Harshit
    Mishra, Varun
    Dasgupta, Avirup
    Lin, Yen-Kai
    Kao, Ming-Yen
    Chauhan, Yogesh Singh
    Salahuddin, Sayeef
    Hu, Chenming
    2019 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2019,
  • [46] InAs Nanowire Gate-All-Around MOSFETs by Heterogeneous Planar VLS Growth
    Zhang, Chen
    Choi, Wonsik
    Mohseni, Parsian
    Li, Xiuling
    2015 73RD ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2015, : 181 - 182
  • [47] InAs Gate-all-around Nanowire MOSFETs by Top-down Approach
    Wu, H.
    Lou, X. B.
    Si, M.
    Zhang, J. Y.
    Gordon, R. G.
    Tokranov, V.
    Oktyabrsky, S.
    Ye, P. D.
    2014 72ND ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2014, : 213 - +
  • [48] GeSn Vertical Gate-all-around Nanowire n-type MOSFETs
    Junk, Yannik
    Frauenrath, Marvin
    Han, Yi
    Diaz, Omar Concepcion
    Bae, Jin-Hee
    Hartmann, Jean-Michel
    Gruetzmacher, Detlev
    Buca, Dan
    Zhao, Qing-Tai
    ESSDERC 2022 - IEEE 52ND EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2022, : 364 - 367
  • [49] Detailed characterisation of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures
    Boudier, D.
    Cretu, B.
    Simoen, E.
    Veloso, A.
    Collaert, N.
    SOLID-STATE ELECTRONICS, 2018, 143 : 27 - 32
  • [50] Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature
    Sekiguchi, Shohei
    Ahn, Min-Ju
    Mizutani, Tomoko
    Saraya, Takuya
    Kobayashi, Masaharu
    Hiramoto, Toshiro
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2021, 9 : 1151 - 1154