On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture

Although adaptive strategies based on the Measure-and-Control (M&C) design paradigm have been proven to be effective methods to achieve aging resilient circuits, their implementation requires accurate monitoring architectures and integrated aging sensors. This paper presents a new on-chip, fully digital monitoring architecture for tracking BTI-induced aging effects on digital ICs. The proposed solution is based on delay-to-threshold coherency of MOS devices and measures differential delay across pass-transistor chains. The aging monitor is conceived and designed as a self-contained standard gate consisting of reference and under stress sensors with embedded measurement circuitries and a control structure for data capturing. To guarantee independent measurements of both Positive- and Negative-BTI, two separate aging sensor blocks are used. Detailed SPICE simulations conducted for a low-power 40nm CMOS technology indicates the actual capability of the proposed circuit to capture BTI-induced aging.