Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the preprocessing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2(n)+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2(n) +1) adder design shows a 24.5% saving in area-delay-product (ADP).