An efficient scan tree design for test time reduction

被引：0

作者：

Bonhomme, Y ^{[1
]}

Yoneda, T ^{[1
]}

Fujiwara, H ^{[1
]}

Girard, P ^{[1
]}

机构：

[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Nara, Japan

来源：

ETS 2004: NINTH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS | 2004年

关键词：

DfT; scan testing; scan tree;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a new scan tree architecture for test application time reduction. This technique is based on a dynamic reconfiguration mode allowing one to reduce the dependence between the test set and the final scan tree architecture. The proposed method includes two different configuration modes: the scan tree mode and the single scan mode. The proposed method does not require any additional input or output. Experimental results show up to 95% of test application time saving and test data volume reduction in comparison with a single scan chain architecture.

引用

页码：174 / 179

页数：6

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