共 50 条
- [31] Energy-Efficient Write Circuit in STT-MRAM Based Look-Up Table (LUT) Using Comparison Write Scheme PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017), 2017, : 288 - 289
- [32] Proactive Dead Block Eviction for Reducing Write Latency in STT-MRAM Caches 2021 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC), 2021,
- [33] Power-Aware Voltage Tuning for STT-MRAM Reliability 2015 20TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2015,
- [34] Device/Circuit/Architecture Co-Design of Reliable STT-MRAM 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 1437 - 1442
- [35] Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), 2018, : 386 - 389
- [40] STT-MRAM memories for loT applications: challenges and opportunities at circuit level and above 2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2017,